The present invention relates to semiconductor devices such as diodes. FIG. 25 is a cross sectional view of a conventional pin diode. Referring now to FIG. 25, the conventional pin diode includes a first n-type semiconductor layer working as an n-type cathode layer 55 with low specific resistance, and a very resistive second n-type semiconductor layer grown epitaxially on the first n-type semiconductor layer. The surface of the second n-type semiconductor layer is mirror finished, a thermal oxide film is coated on the mirror finished surface of the second n-type semiconductor layer, the thermal oxide film is patterned, and a p-type anode layer 51 is formed in the surface portion of the second n-type semiconductor layer. The portion of the second n-type semiconductor layer, where no p-type anode layer 51 is formed, works as an n-type drift layer 58. Thus, an epitaxial substrate 200 is obtained. A heavy metal such as platinum is diffused for controlling the carrier lifetime. An anode electrode 56 and a cathode electrode 57 are formed by metallizing the surface of p-type anode layer 51 and the other surface (back surface) of n-type cathode layer 55.
Although not illustrated, an FZ substrate (bulk substrate) and such another type of substrate are used in substitution for epitaxial substrate 200 described above, and the constituent semiconductor layers are formed by ion implantation and by subsequent thermal drive. In this case, a p-type anode layer is formed in one surface portion of an n-type semiconductor substrate by diffusion, and an n-type cathode layer is formed in another surface portion of the n-type semiconductor substrate by ion implantation and by subsequent thermal derive. The portion of the n-type semiconductor substrate, where neither p-type anode layer nor n-type cathode layer is formed, works as an n-type drift layer.
After diffusing a heavy metal such as platinum for controlling the carrier lifetime, an anode electrode and a cathode electrode are formed on the p-type anode layer 51 and n-type cathode layer 55, respectively, by metalization.
When the conventional pin diode used widely in these days switches from the ON-state to the OFF-state, a high transient current, the so-called reverse recovery current, flows in the opposite direction. The electrical loss, that is the product of the high reverse recovery current and the reverse recovery voltage, is high. It is very necessary to reduce the reverse recovery loss and to increase the switching speed of the diodes.
During reverse recovery, the electrical duties such as the applied voltage, the current and the losses are heavier than those in the steady state. Increase of the steady state current or increase of the voltage in the reverse blocking state causes heavy electrical duties, further causing breakdown of the diode sometimes. For obtaining a very reliable diode for electric power use, it is very necessary to improve the reverse recovery withstanding capability so that the diode may endure the heavy electrical duties.
To improve the reverse recovery characteristics and the reverse recovery withstanding capability, control of the minority carrier lifetime using heavy metal diffusion or electron beam irradiation is employed widely in these days. By shortening the minority carrier lifetime, the total carrier concentration in the steady state is reduced, the concentration of the carriers swept out during reverse recovery by the expanding space charge region is reduced, the reverse recovery time is shortened, the peak reverse recovery current is reduced, and the reverse recovery charge amount is reduced so that the reverse recovery loss may be reduced.
By reducing the hole concentration, the strength of the electric field caused during reverse recovery by the holes flowing through the space charge region is relaxed, and the duties caused during the reverse recovery are reduced so that the reverse recovery withstanding capability may be improved and the diode may not be broken down.
It is also important to provide the diodes with soft recovery characteristics. For the sake of environmental safety, it has been required to reduce the electromagnetic noises caused from power electronic instruments and apparatuses. One method that meets the demand described above makes the reverse recovery current of the diode behave softly to prevent the reverse recovery current and the reverse recovery voltage from oscillating so that the electromagnetic noises caused by the oscillation of the reverse recovery current or the reverse recovery voltage may be reduced.
One means for providing the diode with soft recovery characteristics is a soft recovery structure that suppresses the efficiency of minority carrier injection from the anode side. Typical diodes having the soft recovery structure include a merged pin/Schottky diode (MPS) disclosed in B. J. Baliga, xe2x80x9cThe Pinch Rectifierxe2x80x9d, IEEE Electron. Dev. Lett., ED-5, p. 194, 1984 and a soft and fast recovery diode (SFD) disclosed in M. Mort, et. al., xe2x80x9cA Novel Soft and Fast Recovery Diode (SFD) with Thin P-layer Formed by Alxe2x80x94Si Electrodexe2x80x9d, Proceedings of ISPSD ""91, pp. 113-117, 1991.
As described in M. Nemoto, et. al., xe2x80x9cAn Advanced FWD Design Concept with Superior Soft Reverse Recovery Characteristicsxe2x80x9d, Proceedings of ISPSD 2000, pp. 119-122, 2000, there exists a tradeoff relation between the soft recovery and the fast and low-loss reverse recovery.
To provide the diode with soft recovery characteristics, the total amount of the carriers accumulated in the drift layer in the ON-state of the diode is increased so that the amount of the minority carriers accumulated on the cathode side may increase. As the amount of the minority carriers accumulated on the cathode side increases, many of the minority carriers may remain on the cathode side while the space charge region is expanding from the anode side to the cathode side at the time of reverse recovery. As the number of the minority carriers remaining on the cathode side while the space charge region is expanding from the anode side to the cathode side increases, the reduction rate of the reverse recovery current dir/dt, the so-called reverse-recovery-current reduction-rate, is reduced.
However, when too many carriers are accumulated in the drift layer in the ON-state of the diode, the reverse recovery loss increases and it takes a long time until the reverse recovery ends; that is the reverse recovery time is elongated. On the other hand, a fast and low-loss diode is obtained by controlling the carrier lifetime, which introduces a lifetime killer uniformly into the drift layer, or by thinning the drift layer to reduce the amount of carriers accumulated in the drift layer in the ON-state of the diode. However, as the amount of carriers accumulated in the drift layer is reduced, the amount of the minority carriers accumulated on the cathode side is also reduced, causing the so-called snappy and hard recovery, in which the reverse-recovery-current reduction-rate dir/dt is large. During the snappy and hard recovery, the reverse recovery voltage and the reverse recovery current sometimes oscillate.
Soft recovery is realized by the low-injection-type diodes, such as the MPS and the SFD disclosed in the Bagalia and Mort references. However, lowering of the breakdown voltage and increase of the leakage current under the applied reverse bias voltage are caused more often in the low-injection-type diodes than in the pin diode having the drift layer of the same thickness due to the Schottky junction or the lightly doped anode layer.
Local lifetime control conducted by irradiating a particle ray of a light ion such as proton and helium causes high manufacturing costs, since the cost of irradiation per a wafer is high. If one tries to reduce the tradeoff relation between the fast and low-loss reverse recover and the soft recovery by employing the low-injection-type diode having the MPS structure or the SFD structure or by thinning the drift layer and by employing the local lifetime control, a space for accumulating enough carriers will not be left on the cathode side of the drift layer, causing hard reverse recovery, in which the reverse recovery current and the reverse recovery voltage oscillate. Furthermore, it will be very difficult to obtain a designed breakdown voltage.
In view of the foregoing, there is a need for a semiconductor device that obviates the problems described above. In particular, there is a need for a semiconductor device that facilitates obtaining a designed breakdown voltage while reducing the tradeoff relation between the fast and low-loss reverse recovery and the soft recovery. The present invention addresses these needs.
According to a first aspect of the invention, there is provided a semiconductor device including: a first semiconductor layer of a first conductivity type having a first major surface and a second major surface; a second semiconductor layer of a second conductivity type on the first major surface of the first semiconductor layer, the second semiconductor layer being doped more heavily than the first semiconductor layer; a third semiconductor layer of the first conductivity type on the second major surface of the first semiconductor layer, the third semiconductor layer being doped more heavily than the first semiconductor layer; and a fourth semiconductor layer of the first conductivity type extending across the first semiconductor layer, the fourth semiconductor layer being spaced apart from the second semiconductor layer and the third semiconductor layer, the fourth semiconductor layer being doped more heavily than the first semiconductor layer.
The fourth semiconductor layer can be formed uniformly across the first semiconductor layer. The fourth semiconductor layer can include a plurality of regions. The impurity concentration in the portion of the first semiconductor layer between the second semiconductor layer and the fourth semiconductor layer can be lower than the impurity concentration in the portion of the first semiconductor layer between the third semiconductor layer and the fourth semiconductor layer.
According to a second aspect of the invention, there is provided a semiconductor device including: a drift layer of a first conductivity type having a first major surface and a second major surface; an anode layer of a second conductivity type on the first major surface of the drift layer, the anode layer being doped more heavily than the drift layer; a cathode layer of the first conductivity type on the second major surface of the drift layer, the cathode layer being doped more heavily than the drift layer; and a buffer layer of the first conductivity type extending across the drift layer, the buffer layer being spaced apart from the anode layer and the cathode layer, the buffer layer being doped more heavily than the drift layer.
The buffer layer can be formed uniformly across the first semiconductor layer. The buffer layer can include a plurality of regions. The impurity concentration in the portion of the drift layer between the anode layer and the buffer layer can be lower than the impurity concentration in the portion of the drift layer between the cathode layer and the buffer layer.
The shortest distance X1 from the pn-junction between the anode layer and the drift layer to the edge of the buffer layer on the side of the anode can be expressed by the following relational expression (1):
0.3xe2x89xa6X1/{(BV xcex5s)/q[(JF/q xcexdsat)+ND]}1/2xe2x89xa61.6xe2x80x83xe2x80x83(1),
where BV is the breakdown voltage of the semiconductor device, xcex5s is the dielectric permittivity of the semiconductor, q is the elementary charge quantity, JF is the rated current density of the semiconductor device, vsat is the carrier saturation velocity, and ND is the concentration of the impurity of the first conductivity type in the drift layer.
More preferably, the shortest distance X1 from the pn-junction between the anode layer and the drift layer to the edge of the buffer layer on the side of the anode can be expressed by the following relational expression (2):
0.8xe2x89xa6X1/{(BV xcex5s)/q[(JF/q xcexdsat)+ND]}1/2xe2x89xa61.2xe2x80x83xe2x80x83(2), 
where, BV is the breakdown voltage of the semiconductor device, xcex5s is the dielectric permittivity of the semiconductor, q is the elementary charge quantity, JF is the rated current density of the semiconductor device, xcexdsat is the carrier saturation velocity, and ND is the concentration of the impurity of the first conductivity type in the drift layer. The thickness Y1 of the buffer layer and the average impurity concentration ND2 of the buffer layer can be related with each other by the following relational expression (3):
Y1/{[X12+2xcex5s(VCC+VPT)/q ND2]1/2xe2x88x92X1}xe2x89xa62xe2x80x83xe2x80x83(3),
where X1 is the shortest distance from the pn-junction between the anode layer and the drift layer to the edge of the buffer layer on the side of the anode, VCC is the half value of the breakdown voltage of the semiconductor device, VPT is the voltage, at which the depletion layer contacts the buffer layer of the first conductivity type, xcex5s is the dielectric permeability of the semiconductor, and q is the elementary charge quantity.
The buffer layer can include a plurality of selectively formed island-shaped regions. The buffer layer can include a plurality of selectively formed stripe-shaped regions.
According to a third aspect of the invention, there is provides a semiconductor device including: a bulk wafer including a first drift layer of a first conductivity type, the bulk wafer having a first major surface and a second major surface; a buffer layer of the first conductivity type on the first major surface of the bulk wafer, the buffer layer being doped more heavily than the first drift layer by implanting an impurity of the first conductivity type; a second drift layer of the first conductivity type epitaxially grown on the buffer layer, the second drift layer being doped more lightly than the buffer layer; an anode layer formed by implanting an impurity of a second conductivity type into the second drift layer; an anode electrode on the anode layer; a cathode layer on the surface of the bulk wafer exposed by grinding back the bulk wafer for a predetermined depth from the second major surface thereof, the cathode layer being doped more heavily than the first drift layer by implanting an impurity of the first conductivity type; and a cathode electrode on the cathode layer.
According to a fourth aspect of the invention, there is provided a method of manufacturing a semiconductor device, the method including the steps of: implanting an impurity of a first conductivity type into the first major surface of a bulk wafer including a first drift layer of the first conductivity type, by which to form a buffer layer of the first conductivity type doped more heavily than the first drift layer; growing epitaxially a second drift layer of the first conductivity type on the buffer layer, the second drift layer being doped more lightly than the buffer layer; implanting an impurity of a second conductivity type into the second drift layer, by which to form an anode layer; forming an anode electrode on the anode layer; grinding back the bulk wafer from the second major surface thereof, by which to remove the portion of the bulk wafer for a predetermined depth from the second major surface; implanting an impurity of the first conductivity type to the surface of the bulk wafer exposed by the grinding back, by which to form a cathode layer doped more heavily than the first drift layer; and forming a cathode electrode on the cathode layer.